Solutions for implementing voice and/or image recognition tasks in an integrated circuit face challenges of losing data precision or accuracy due to limited resources in the integrated circuit. For example, a single low-power chip (e.g., ASIC or FPGA) for voice or image recognition tasks in a mobile device is typically limited in chip size and circuit complexity by design constraints. A voice or image recognition task implemented in such a low-power chip cannot use data that has the same numeric precision, nor can it achieve the same accuracy as when performing the tasks in a processing device of a desktop computer. For example, an artificial intelligence (AI) integrated circuit (i.e., a chip) in a mobile phone may have an embedded cellular neural network (CeNN) architecture that has only 5 bits per channel to represent data values, whereas CPUs in a desktop computer or a server in a cloud computing environment use a 32-bit floating point or 64-bit double-precision floating point format. As a result, image or voice recognition models, such as a convolutional neural network, when trained on desktop or server computers and transferred to an integrated circuit with low bit-width or low numeric precision, will suffer a loss in performance.
This patent disclosure is directed to systems and methods for addressing the above issues and/or other issues.